HDL Coder for Software Defined Radio

Generate Open Source FPGA code from MATLAB and Simulink


This training curriculum is designed to provide a strong understanding of the concepts outlined below.

Each day is built for 7 hours of content. Timing information provided below is approximate and may be adjusted dynamically by instructors to meet class needs. 

Examples and exercises are built into the material and hands-on time will be provided throughout the training to illustrate concepts and provide practice time. All courses of this training are derived from proven course content and will include detailed instructions and vetted examples and exercises. The content will be presented in a hands-on manner and attendees will get plenty of opportunities to work on course exercises to reinforce concepts.

Location and Class Size

As soon as we have 15 signed up, registration will close and a wait list will start. If there's strong response, then we'll organize another class. 

The training will be delivered virtually. The last page of this document lists the tools we use for our virtual trainings. We will hold an hour-long systems check the day before the event for all attendees so that everyone can test their connectivity before the training day. All attendees should perform the systems check from the setup they will be using for the training. 

For more information on our virtual training platform, please visit: https://www.mathworks.com/videos/advantages-of-virtual-matlab-training-1595412672535.html


Training dates are 1-5 May 2023.
Instruction will be held 0900 - 1700 US Pacific with scheduled breaks. The longest break is mid-day.  


Day 0 - Systems Check 

Instructions will be sent to the email you give us. It should not take long to check out your system on Day 1 to make sure you can access the lectures and labs.

Day 1 - Generating HDL Code from Simulink & DSP for FPGAs

Preparing Simulink Models for HDL Code Generation (1.0 hrs)

Prepare a Simulink model for HDL code generation. Generate HDL code and testbench for simple models requiring no optimization.

•Preparing Simulink models for HDL code generation

•Generating HDL code

•Generating a test bench

•Verifying generated HDL code with an HDL simulator

Fixed-Point Precision Control (2.0 hrs)

Establish correspondence between generated HDL code and specific Simulink blocks in the model. Use Fixed-Point Tool to finalize fixed point architecture of the model.

•Fixed-point scaling and inheritance

•Fixed-Point Designer workflow

•Fixed-Point Tool

•Fundamental adders and multiplier arrays

•Division and square root arrays

•Wordlength issues and Fixed-point arithmetic

•Saturation and wraparound.

•Overflow and underflow

Optimizing Generated HDL Code (4 hrs)

Use pipelines to meet design timing requirements. Use specific hardware implementations and share resources for area optimization.

•Generating HDL code with the HDL Workflow Advisor

•Meeting timing requirements via pipelining

•Choosing specific hardware implementations for compatible Simulink blocks

•Sharing FPGA/ASIC resources in subsystems

•Verifying that the optimized HDL code is bit-true cycle-accurate

•Mapping Simulink blocks to dedicated hardware resources on FPGA

Day 2 - DSP for FPGAs

Signal Flow Graph (SFG) Techniques (SFG) Techniques and high-speed FIR design (2.0 hrs)

Review the representation of DSP algorithms using signal flow graph. Use the Cut Set method to improve timing performance. Implement parallel and serial FIR filters.

•DSP/Digital Filter Signal Flow Graphs

•Latency, delays and "anti-delays"!

•Re-timing: Cut-set and delay scaling

•The transpose FIR

•Pipelining and multichannel architectures

•SFG topologies for FPGAs

•FIR filter structures for FPGAs

Multirate Signal Processing for FPGAs (4.0 hrs)

Develop polyphase structure for efficient implementation of multirate filters. Use CIC filter for interpolation and decimation.

•Upsampling and interpolation filters

•Downsampling and decimation filters

•Efficient arithmetic for FIR implementation

•Integrators and differentiators

•Half-band, moving average and comb filters

•Cascade Integrator Comb (CIC) Filters (Hogenauer)

•Efficient arithmetic for IIR Filtering

CORDIC Techniques and channelizers (2.0 hrs)

Introduce CORDIC algorithm for calculation of various trigonometric functions.

•CORDIC rotation mode and vector mode

•Compute cosine and sine function

•Compute vector magnitude and angle

•Architecture for FPGA implementation


Day 3 - Programming Xilinx Zynq SoCs with MATLAB and Simulink & Software-Defined Radio with Zynq using Simulink

IP Core Generation and Deployment (2.0 hrs)

Use HDL Workflow Advisor to configure a Simulink model, generate and build both HDL and C code, and deploy to Zynq platform.

•Configuring a subsystem for programmable logic

•Configuring the target interface and peripherals

•Generating the IP core and integrating with SDK

•Building and deploying the FPGA bitstream

•Generating and deploying a software interface model

•Tuning parameters with External Mode

Model Communications System using Simulink (1.5 hrs)

Model and simulate RF signal chain and communications algorithms.

•Overview of software-defined radio concepts and workflows

•Model and understand AD9361 RF Agile Transceiver using Simulink

•Simulate a communications system

•Use a Transmitter, AD9361 Transceiver, channel and Receiver

Day 4 - Programming Xilinx Zynq SoCs with MATLAB and Simulink & Software-Defined Radio with Zynq using Simulink (continued)

Implement Radio I/O with ADI RF SOM and Simulink (1.5 hrs)

Verify the operation of baseband transceiver algorithm using real data streamed from the AD9361 into MATLAB and Simulink.

•Overview of System object and hardware platform

•Set up ADI RF SOM as RF front-end for over-the-air signal capture or transmission

•Perform baseband processing in MATLAB and Simulink on captured receive signal

•Configure AD9361 registers and filters via System object

•Verify algorithm performance for real data versus simulated data

Prototype Deployment with Real-Time Data via HW/SW Co-Design (2.0 hrs)

Generate HDL and C code targeting the programmable logic (PL) and processing system (PS) on the Zynq SoC to implement TX/RX.

•Overview of Zynq HW/SW co-design workflow

•Implement Transmitter and Receiver on PL/PS using HW/SW co-design workflow

•Configure software interface model

•Download generated code to the ARM processor and tune system parameters in real-time operation via Simulink

•Deploy a stand-alone system

How Can I Come up to Speed?

You do need a basic understanding of digital communications and FPGA technology. If the terms in the class outline are completely unfamiliar to you, then it's not going to be nearly as fun as it could be. If you want to do this sort of work for open source digital radio, then get in touch at hello at openresearch dot institute and let's talk about how we can help.

If you need to come up to speed with or refresh your knowledge of MATLAB and Simulink, then start now at https://matlabacademy.mathworks.com/

1) Take the MATLAB and Simulink On-Ramps. Short, powerful, and useful classes that will make it possible for you to use the tools in this class with confidence. 

2) Take the MATLAB and Simulink Fundamentals. Longer and more involved content, these will get you up to the point where you can take the fullest advantage of this class. 


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